The present invention relates to memory circuits, and more specifically to redundant type memory circuits having redundant structure.
The memory capacity of semiconductor memories has been recently increased, but the increase in the memory capacity has resulted in low fabrication yield due to the low probability of all circuit elements on such a dense structure being fabricated without defect. Hence, it has become difficult to obtain a memory in which all the constituent elements are good.
To reduce the above problem, memories having a redundant structure have been developed and are widely utilized. In a memory having a redundant structure, a redundant array of memory cells is provided in addition to a normal array of memory cells. If a cell or cells in the normal array are faulty or defective, such defective cells are functionally replaced by good cells in the redundant array, so that a functionally good memory can be obtained even though defects may be present in the normal array. In such a redundant type memory, the replacement of a defective cell in the normal array with a good cell in the redundant array is typically conducted by replacing a column or a row including the defective cell in the normal array with a column or a row of good cells in the redundant array. For achieving the above replacement of columns or rows, a programmable type redundant decoder circuit is provided to the redundant array to operatively select columns or rows of the redundant array. Information as to the address of the replaced columns or rows is stored by the programmable type redundant decoder. When a defective column or a defective row including the defective cell in the normal array is addressed from the outside, the programmable type redundant decoder circuit operates to select one column or one row in the redundant array while accessing of the defective column or defective row in the normal array is inhibited by an inhibit signal which is generated in response to a selection output of the redundant decoder circuit. Namely, when the redundant cell array is accessed by the redundant decoder, a normal decoder circuit provided to the normal array is inhibited from selecting the normal array.
In order to allow the above operation, it is inevitably necessary to control the normal decoder circuit after the establishment of the state of the redundant decoder circuit. Therefore, in the redundant type memory, the redundant decoder circuit is first activated, and then the normal decoder is activated only when the any column or row in the redundant array is not selected by the redundant decoder circuit, and the inhibit signal is not generated. Therefore, a clock generator employed in the redundant type memory is designed to generate a first clock for enabling the redundant decoder circuit, and thereafter generate a second clock for enabling the normal decoder circuit. However, even though all the elements in the normal array are good and the redundant decoder circuit is programmed not to select the redundant array, the activation of the normal decoder circuit is still performed by the second clock which is generated with a delayed time from the occurrence of the first clock, and hence operation of the memory is unnecessarily delayed, resulting in a low speed operation.